1. Field of the Invention
The present invention relates in general to the fabrication of semiconductor devices, and more particularly to a simplified method for forming a self-aligned contact hole.
2. Description of the Related Arts
Self-alignment is a technique in which multiple levels of regions on the wafer are formed using a single mask, thereby eliminating the alignment tolerance required by additional masks. This powerful approach is being used more often as circuit sizes decrease. Self-aligned contacts are often used in memory cells where contacts are limited only by the spacers and field oxide bird's beak or a contact window landing pad. Therefore, the mask contact window can be oversized relative to the contact area underneath, and no contact borders are needed, resulting in significant space saving. Referring to FIGS. 1A-1E, a conventional process of forming a self-aligned contact hole is illustrated in cross-sectional views. The process will be described as follows.
FIG. 1A shows a semiconductor substrate 10 having two closely spaced field effect transistors with gate electrodes 14, source/drain diffusion regions 18, and gate oxides 12. The gate electrodes 14, commonly consisting of polysilicon and silicide, are capped with an insulator 16 of silicon nitride. Next, a thin oxide layer 20 is formed over the substrate surface and on the sidewalls of the gate electrode 14 by rapid thermal oxidation at about 800 to 1100.degree. C.
Referring to FIG. 1B, a conformal layer of silicon nitride 22 having a thickness of about 100 to 600 .ANG. is deposited over the substrate surface using low pressure chemical vapor deposition (LPCVD). The conformal silicon nitride layer 22 is anisotropically etched to form nitride spacers 22a on the sidewalls of the gate electrodes 22 and the cap layers 16, as shown in FIG. 1C. Then, the thin oxide layer on the substrate surface is removed by HF solution to expose the diffusion region 18.
Referring to FIG. 1D, a conformal layer of etch barrier material 24 is deposited over the diffusion region 18, the cap layers 16, and the sidewall spacers 22a. The barrier layer is typically a silicon nitride layer having a thickness of about 100 to 500 .ANG.. A layer of insulator 26 is deposited over the substrate as inter-layer dielectric (ILD) and is preferably planarized. The insulating layer 26 may consist of one or more dielectric depositions of spin on glass (SOG), silicon oxide, borophosphosilicate (BPSG), and so on.
Referring to FIG. 1E, using a photoresist mask 28, a contact hole 29 is etched in the insulating layer 26 with the barrier layer 24 serving as an etch stop, which is finally removed to expose the diffusion region 18. The etching of the insulating layer 26 is selective to the capping layers 16 and sidewall spacers 22a encapsulating the gate electrodes 14 so that the contact hole is self-aligning in nature.
The fabricating method described above, however, requires complicated processes. For example, two depositions of silicon nitride are required for forming the conformal layer 22 and the barrier layer 24, respectively. Besides, the two layers are to be etched individually. The conformal nitride layer 22 is etched to form nitride spacers 22a, and the barrier layer 24 is etched to reveal the underlying diffusion region 18 after the contact hole etching. Thus, improvements are needed to eliminate process steps so as to reduce the manufacturing cost and to increase the throughput.